The guy who created the DCC++ system explains it in pretty good detail in the video below...
Steve S
You are correct for the '1' bit (for the nmoinal value, each half is actually allowed to be between 55 and 61 microseconds); however, not for the '0' bit. Each half of the '0' bit shall nominally be equal to or greater than 100 microseconds. Each '0' bit half cycle shall have a duration of between 95 and 9900 microseconds and the two halves do not have to be equal (to allow for "zero bit stretching" to run an analog loco).
http://www.nmra.org/sites/default/files/standards/sandrp/pdf/s-9.1_electrical_standards_2006.pdf
I found an answer to my question:
Digital 1s are represented by 1 cycle at 116 microseconds and 0s by 1 cycle lessthan or equal to 232 microseconds. Each cycle consists of equal time half cycles.
I understand the frequency of DCC data packets should be between 5-30 ms between packets (as listed in the spec). What is the frequency of the bits within the packets? ie. What is the duration of each bit (0/1)?